Products > VPX > Pre-configured Systems -> Network Centric Secure Router + 3+1 CPU System
Network Centric Secure Router + 3 CPU System
Due to the high heat generated by the CPU cards, this system is only available in the sealed – forced air cooled version (ATR Style) 3U VPX chassis “Crosswind 600” . Ruggedized and sealed to IP65. This unit can use void fillers and GORE brand vents depending on the deployment environment.
- PCIe Gen.3 x16 per slot, 2x8 possible
- Gen.3 PCIe Switch on backplane mezzanine
- 3x Intel I7
- 1x Intel Atom
- Rugged Router 8 Port (FIPS)
The system is 3U VPX based. It consists of four CPU modules with a 512GB SSD on each module, a power supply module [SMART.PSU] Technology explained, a Juniper Networks LN1000 rugged router and a PCIe High Speed RAID SSD module with up to 4TB.
The system utilizes a 26-port layer 2/3 Gigabit Ethernet switch with embedded 32-bit CPU.
It supports combinations of up to 26 SGMII ports consisting of 12 GbE Cu PHYs, 12 SGMII interfaces, two of which support 1G/2.5G, and up to three QSGMII ports. One of the SGMII ports can be dedicated to the CPU for packet insertion and extraction. The devices meet IEEE 802.3az requirements for green energy efficient Ethernet.
A powerful embedded 416 MHz MIPS processor 32-bit CPU with DDR2external memory and DMA-based frame extraction and insertion supports timing over packet, Ethernet OAM, and performance monitoring.
A comprehensive application programming interface (API) and software package are provided for Carrier Ethernet applications. The software package integrates easily with third-party software, preserving existing software investments while adding new, enhanced carrier functionality.
I/O configurations
- 12× 1G Cu PHY, 3× QSGMII, 1× SGMII, 1× 1G/2.5G SGMII
- 12× 1G Cu PHY, 10× SGMII, 2× 1G/2.5G SGMII
- 10× 1G Cu PHY, 8× SGMII, 2× 1G.2.5G SGMII Architecture
- Shared memory buffer with per-port and CoS memory management
- 4 Mb packet memory
- Hierarchical MEF compliant policing and scheduling
- 8 priorities and 8 CoS queues per port with strict or deficit-weighted round robin scheduling
- Shaping/policing per queue and per port
- Advanced security and prioritization available through a multistage TCAM engine
- 12× integrated 10/100/1000BASE-T Ethernet copper transceivers (IEEE 802.3ab compliant) with power management cable diagnostics
- Integrated 416 MHz MIPS CPU with DDR2 and serial flash interface
All signals interface with the real world at the front cover of the unit. The unit features an on/off switch, status LEDs and various I/O using circular MIL-DTL-38999 connectors.
Block diagram: Network Centric Secure Router + 3+1 CPU System
PCIe Gen 3 "noStub" routing is used throughout the system to maximize data throughput. Inter-slot high speed communication connections are done on this mezzanine PCB. It is possible to use a Gb Ethernet switch and a serial Rapid I/O switch on this mezzanine, if needed. On this mezzanine card a 3D shock sensor IC is integrated and the values can be read over a I2C bus which is connected to pin outs as per VITA 46 specification.
PCI-Systems is using an unique approach to save valuable slots by using a mezzanine PCB parallel to the backplane. On this mezzanine, all needed switches are placed. For instance PCIe Gen3, Rapid I/O, 10Gb Ethernet. Usually those switches occupy up to 3 valuable slots on the backplane and Gen3 routing is basically not possible because of crosstalk, stubs and losses, using the primary backplane. Also specific interconnections between backplane slots are done on the mezzanine PCB. A very important point is that the high speed switches are located in the middle of the backplane mezzanine PCB, assuring the shortest possible connections to all VPX slots.
For further technical specifications / pin-out tables (eICD) please ask your representative or fill out the request form here.